Title :
The JUMP-1 router chip: a versatile router for supporting a distributed shared memory
Author :
Nishi, Hidetaka ; Nishimura, Kosuke ; Kudoh, T. ; Amano, Hideharu
Author_Institution :
Keio Univ.
Abstract :
JUMP-1 (Japanese Universities MultiProcessor) is currently under development by seven Japanese universities to establish techniques for an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with a reduced hierarchical bit-map directory scheme to achieve cost-effective and high-performance management. Messages for the coherent cache are transferred through a fat tree on the RDT (recursive diagonal torus) interconnection network. The JUMP-1 router supports versatile functions, including combined multicasting and acknowledgement for the reduced hierarchical bit-map directory scheme
Keywords :
cache storage; coherence; distributed memory systems; hierarchical systems; integrated logic circuits; multiprocessor interconnection networks; network routing; switching circuits; tree data structures; JUMP-1 router chip; Japanese Universities Multiprocessor; RDT interconnection network; acknowledgement; coherent cache; distributed shared memory; fat tree; massively parallel processor; message transfer; multicasting; recursive diagonal torus; reduced hierarchical bit-map directory scheme; versatile functions; BiCMOS integrated circuits; Cables; Clocks; Collaboration; Costs; Local area networks; Memory management; Multiprocessor interconnection networks; Prototypes; Read-write memory;
Conference_Titel :
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-3255-5
DOI :
10.1109/PCCC.1996.493628
