Title :
A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAM
Author :
Hardee, K. ; Jones, F. ; Butler, D. ; Parris, M. ; Mound, M. ; Jones, Glenn ; Aldrich, L. ; Taniguchi, Kazuhiro ; Arakawa, Issei
Author_Institution :
United Memories, Colorado Springs, CO, USA
Abstract :
A 0.6V 16Mb embedded DRAM macro is presented as a solution for mobile personal consumer applications. The macro has 128 separate I/Os and employs positive and negative on-chip body bias, boosted and staggered power gating, and Vcc/2 sensing to achieve 205MHz operation with 19.5ns tRC and 39mW operating power.
Keywords :
DRAM chips; cellular arrays; low-power electronics; 0.6 V; 16 Mbit; 205 MHz; 39 mW; boosted power gating; clock frequency; embedded DRAM macro; high bandwidth; low power embedded DRAM; mobile personal consumer application; on-chip body bias; staggered power gating; Batteries; Latches; Logic circuits; Low voltage; MOS devices; Monitoring; Power amplifiers; Random access memory; Regulators; Variable structure systems;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332663
