Title :
A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applications
Author :
Morishita, Fukashi ; Hayashi, Isao ; Matsuoka, Hikari ; Takahashi, Koichi ; Shigeta, Kazuki ; Gyohten, T. ; Niiro, M. ; Okamoto, Mitsuo ; Hachisuka, A. ; Amo, A. ; Shinkawata, H. ; Dosaka, Katsumi ; Arimoto, Keisuke
Author_Institution :
Renesas Technol., Hyogo, Japan
Abstract :
An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13μm low-power process and it achieves 312MHz random cycle operation. Data retention power is 73μW, which is 5% compared to a conventional one.
Keywords :
DRAM chips; cellular arrays; cellular radio; low-power electronics; notebook computers; 16 Mbit; 312 MHz; cellular phone; data retention scheme; embedded DRAM macro; low-power process; negative edge transmission scheme; power-down mode; random-cycle embedded; self-adjustable timing control; Cellular phones; Circuits; Delay effects; Gate leakage; Personal digital assistants; Phased arrays; Random access memory; Signal generators; Timing; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332664
