Title :
Split inherent-capacitive load buffer
Author :
Vemuru, Srinivasa R
Author_Institution :
Dept. of Electr. Eng., City Univ. of New York, NY, USA
Abstract :
CMOS buffers consist of a series of tapered inverters with each inverter driving a larger inverter. We split the inherent capacitance of the driving inverter stage of a CMOS buffer into two components (Cx and Cz), and show that the optimum taper factor is a function of Cx/Cz ratio. Overall buffer propagation delay and output transition time of the new buffer are smaller with a small increase in area and power dissipation
Keywords :
CMOS integrated circuits; buffer circuits; capacitance; logic gates; CMOS buffers; area; output transition time; power dissipation; propagation delay; split inherent-capacitance load model; tapered inverters; Capacitance; Circuits; Cities and towns; Conductors; Inverters; Load modeling; MOS devices; Predictive models; Propagation delay; SPICE;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580678
