Title :
A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipelining
Author :
Barth, Jens ; Anand, Dhananjay ; Dreibelbis, J. ; Fifield, J. ; Gorman, Kevin ; Nelms, M. ; Pomichter, G. ; Pontius, D.
Author_Institution :
IBM Microelectron., Burlington, VT, USA
Abstract :
A 500MHz compiled DRAM macro fabricated in 90nm logic-based process is presented. The random bank cycle is reduced by 50% over the previous generation through segmentation and a direct write scheme. 500MHz operation is achieved with a configurable 4-stage pipeline.
Keywords :
DRAM chips; cellular arrays; memory architecture; 500 MHz; column redundancy solution; configurable 4-stage pipeline; direct write; logic-based process; multi-banked compilable DRAM macro; programmable pipelining; random bank cycle; Application specific integrated circuits; Availability; Foundries; Interleaved codes; Kernel; Logic arrays; Microelectronics; Pipeline processing; Random access memory; Writing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332665
