A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

Author

Sang-Bo Lee ; Seong-Jin Jang ; Sang-Jun Hwang ; Seong-Ho Cho ; Min-Sang Park ; Ho-Kyoung Lee ; Woo-Jin Lee ; Won-Hwa Shin ; Jong-Soo Lee ; Yun-Sik Park ; Seok-Won Hwang ; Young-Hyun Jun ; Soo-In Cho

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

210

Abstract

An 8M×32 graphic DOR (GDDR) SDRAM operating at 800MHz is introduced. It needs a large number of CAS latencies(CLs) to support the frequency range of 300 to 800MHz. A wave-pipelined CL control circuit is proposed to provide stable operation for the wide number of CLs. The gapless write-to-read scheme is applied to improve the efficiency of the data bus at high-speed operation with large number of CLs.

Keywords

CMOS memory circuits; DRAM chips; cache storage; low-power electronics; pipeline processing; 800 MHz; CMOS process; data bus efficiency; double-data-rate SDRAM; gapless write-to-read scheme; graphic DOR SDRAM; high-speed operation; partial activation command circuit; peak power consumption; stable operation; wave-pipelined CAS latency control; Clocks; Content addressable storage; Counting circuits; Delay; Energy consumption; Flip-flops; Frequency; Registers; SDRAM; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332668

Filename

1332668