DocumentCode :
3412748
Title :
Vector-radix IDCT implementation for MPEG decoding
Author :
Zhou, Minli
Author_Institution :
TSE Corp., Dallas, TX, USA
fYear :
1995
fDate :
18-22 Sep 1995
Firstpage :
75
Lastpage :
78
Abstract :
This paper introduces a hardware architecture and VHDL implementation of a Vector-Radix DCT/IDCT algorithm. The architecture provides a true generic structure for both DCT and IDCT. For MPEG-1 video IDCT, it can run at a low frequency of 27 MHz to meet the data rate at SIF resolution with the additional capability of handling part of an inverse quantization task. For MPEG-2 at MP@ML, the IDCT can be carried out at 81 MHz clock rate. The 8×8 implementation can also be easily upgraded to handle any N×N transform of power of two
Keywords :
decoding; discrete cosine transforms; hardware description languages; inverse problems; video coding; 27 MHz; 81 MHz; MPEG video decoding; MPEG-1; MPEG-2; SIF resolution; VHDL; hardware architecture; inverse quantization; vector-radix DCT/IDCT algorithm; Clocks; Decoding; Digital signal processing; Discrete cosine transforms; Discrete transforms; Frequency domain analysis; Hardware; Multimedia systems; Signal analysis; Signal processing algorithms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
ISSN :
1063-0988
Print_ISBN :
0-7803-2707-1
Type :
conf
DOI :
10.1109/ASIC.1995.580685
Filename :
580685
Link To Document :
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