DocumentCode
3412763
Title
A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application
Author
Kyu-Hyoun Kim ; Jung-Bae Lee ; Woo-Jin Lee ; Byung-Hoon Jeong ; Geun-Hee Cho ; Jong-Soo Lee ; Gyung-Su Byun ; Changhyun Kim ; Young-Hyun Jun ; Soo-In Cho
Author_Institution
Samsung Electron., Hwasung, South Korea
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
212
Abstract
A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the charge pump, is proposed. It makes the output of the charge pump virtually grounded, to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a speed of 1.4 Gb/s.
Keywords
DRAM chips; digital phase locked loops; timing circuits; 1.4 Gbit/s; DLL; PLL; charge pump nonideal characteristics; current mismatch; digital locking information; duty-cycle corrector; high-speed DRAM; low duty error; low phase error; second order charge-pump scheme; timing circuits; virtually grounded charge pump output; Capacitors; Charge pumps; Counting circuits; Detectors; Energy consumption; Frequency; Phase detection; Random access memory; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332669
Filename
1332669
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