Title :
A parallel 2 Gops/s image convolution processor with low I/O bandwidth
Author :
Öwall, Viktor ; Torkelson, Mats ; Egelberg, Peter
Author_Institution :
Dept. of Appl. Electron., Lund Univ., Sweden
Abstract :
A customized image processor for real time convolution of an image has been developed. Image convolution requires an extensive amount of calculation capacity and I/O communication which is hard to sustain with standard processors in real time. Therefore, a customized processor has been designed with a tailored architecture. The processors have a total sustained calculation capacity of >2G arithmetic operations/s at 20 MHz clock frequency, surpassing that of TMS320C80 for this application due to the tailored architecture
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; convolution; digital signal processing chips; image processing; image processing equipment; parallel architectures; real-time systems; 20 MHz; CMOS DSP chip; customized processor; low I/O bandwidth; parallel image convolution processor; real time convolution; tailored architecture; Arithmetic; Bandwidth; Computer vision; Convolution; Digital signal processing chips; Hardware; Kernel; Libraries; Process design; Signal processing algorithms;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580688
