DocumentCode
3412844
Title
Inverter-based models for current analysis of CMOS logic circuits
Author
Nabavi-Lishi, A. ; Rumin, N.C.
Author_Institution
Dept. of Electr. Eng., Tarbeiat Modaress Univ., Tehran, Iran
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
13
Abstract
This paper presents techniques for reducing CMOS gates to equivalent inverters for current and delay analysis. These do not assume a single input switching, and they account for the speed of the input transitions, as well as for the relative positions of the inputs in series-connected MOSFETs. The resulting inverters have been tested using previously published current analysis techniques. The gate reduction time is small compared to that for determining the current, and there is no significant effect on the accuracy
Keywords
CMOS logic circuits; delays; equivalent circuits; integrated circuit modelling; logic gates; CMOS logic circuits; current analysis; delay analysis; gate reduction time; input transitions; inverter-based models; series-connected MOSFETs; CMOS logic circuits; CMOS technology; Current supplies; Delay; Inverters; MOSFETs; Semiconductor device modeling; Switches; Tin; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408743
Filename
408743
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