Fault modeling and mapping for quantum-dot cellular automata (QCA) designs

This paper addresses the issue of fault modeling and mapping between a design done at the CMOS gate-level and one done using QCA technology. Since QCA and CMOS gate-level defects differ completely, it is important to investigate the mapping between classical single stuck-at fault (SSF) modeling and QCA defect and failure modes. This paper suggests a methodology in which fault modeling for a QCA circuit can be inferred from the SSF modeling of its CMOS gate-level representation. Cadence NCLaunch was used for SSF modeling while QCADesigner was used for QCA circuit simulation and fault modeling.