Title :
110Gb/s multiplexing and demultiplexing ICs
Author :
Suzuki, Yuya ; Yamazaki, Z. ; Wada, Sho ; Uchida, Hironaga ; Tanaka, Shoji ; Hida, Hirotaka
Author_Institution :
NEC Corp., Tsukuba, Japan
Abstract :
A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.
Keywords :
III-V semiconductors; bipolar logic circuits; demultiplexing equipment; flip-flops; high-speed integrated circuits; impedance matching; indium compounds; multiplexing equipment; 110 Gbit/s; 120 Gbit/s; HBT process; InP; asymmetrical latch flip-flop; broadband impedance matching; demultiplexing IC; direct drive series-gating configuration selector; high-speed transmission; inverted microstrip lines; large driving capability; multiplexing IC; Clocks; Demultiplexing; Frequency; HEMTs; Heterojunction bipolar transistors; Impedance matching; Indium phosphide; Integrated circuit interconnections; Latches; National electric code;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332679
