Extraction of source/drain resistance from layout for 0.5 μm non-salicide process technology

Scaling of non-salicide processes to the deep sub-micron regime will require that circuit simulators take into account sheet resistances. An accurate simulator to extract source and drain resistances from the circuit layout has been developed. The degradation of saturation drain current is most significant for increased parasitic source resistance, and the reduction of linear drain current is significantly affected by increased parasitic drain resistance