Title :
Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic
Author :
Carlough, S. ; Steidl, S. ; Airapetian, A. ; Garg, A. ; Maier, C. ; Campbell, P. ; Greub, H.J. ; McDonald, J.F.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
Soft-programmable logic is increasingly used to emulate and verify CMOS designs before fabrication. The F-RISC emulator uses this technology to emulate and verify a multichip GaAs RISC processor. An essential part of the F-RISC emulator is the mapping of the differential CML GaAs libraries to the Xilinx FPGA libraries. The emulator helped to detect several design errors
Keywords :
III-V semiconductors; bipolar digital integrated circuits; circuit CAD; current-mode logic; gallium arsenide; heterojunction bipolar transistors; integrated circuit design; logic CAD; microprocessor chips; programmable logic devices; reduced instruction set computing; F-RISC emulator; HBT circuits; RISC processor; Xilinx FPGA libraries; design errors; design verification; differential CML libraries; multichip processor; soft-programmable logic; CMOS logic circuits; Delay; Emulation; Field programmable gate arrays; Gallium arsenide; Heterojunction bipolar transistors; Libraries; Logic design; Programmable circuits; Reduced instruction set computing;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580706
