Title :
A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS
Author :
Yamazaki, D. ; Yamamoto, Takayuki ; Nomura, Hideyuki ; Hashimoto, Koji ; Onodera, Hidetoshi
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
This paper describes a 25 GHz clock buffer and 50 Gb/s 2-to-1 selector, which are implemented in 90 nm CMOS using 48 nm transistors, and operate off a 1 V supply. An inductor-peaked CMOS inverter is employed for the clock buffer. The selector is equipped with a tail transistor whose gate is switched by the rail-to-rail clock signal produced by the buffer.
Keywords :
CMOS logic circuits; buffer circuits; demultiplexing equipment; logic gates; 1 V; 25 GHz; 48 nm; 50 Gbit/s; 90 nm; CMOS; clock buffer; inductor-peaked CMOS inverter; rail-to-rail clock signal; selector switched gate tail transistor; two-to-one selector; Bandwidth; CMOS logic circuits; CMOS technology; Circuit testing; Clocks; Frequency; Inductors; Inverters; MOS devices; Parasitic capacitance;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332683
