DocumentCode
3413074
Title
A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise
Author
Seung-Jun Bae ; Hyung-Joon Chi ; Young-Soo Sohn ; Hong-June Park
Author_Institution
Pohang Inst. of Sci. & Technol., South Korea
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
244
Abstract
A 2Gb/s integrating 2-tap decision feedback equalizer receiver is implemented in a 0.25μm CMOS process to reduce high- and low-frequency noise for multi-drop single-ended signaling system. Voltage margin is enhanced by 110%(90%) for a stubless channel at 2Gb/s (an SSTL channel at 1.2Gb/s).
Keywords
CMOS analogue integrated circuits; decision feedback equalisers; integrating circuits; radio receivers; 2 Gbit/s; 2-tap DFE receiver; CMOS process; ISI component; decision feedback equalizer receiver; integrating receiver; interleaving receiver; look-ahead receiver; multidrop single-ended signaling systems; sense-amp-based flip-flop; stubless channel; voltage margin; Capacitance; Circuits; Communication system signaling; Crosstalk; Decision feedback equalizers; Intersymbol interference; Low-frequency noise; Noise generators; Noise reduction; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332685
Filename
1332685
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