An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

Author

Jaussi, J.E. ; Balamurugan, Ganesh ; Johnson, Daniel R. ; Casper, Bryan K. ; Martin, Andrew ; Kennedy, J.T. ; Shanbhag, Naresh ; Mooney, Randy

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

246

Abstract

An 8Gb/s binary source-synchronous I/O link with adaptive receiver-equalization, offset cancellation and clock deskew is implemented in 0.13μm CMOS. The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. On-die adaptation logic determines optimal receiver settings.

Keywords

CMOS analogue integrated circuits; FIR filters; adaptive equalisers; discrete time filters; high-speed integrated circuits; transceivers; 8 Gbit/s; CMOS analog equalizer; FIR filter; adaptive receiver equalization; clock deskew; clock generator; discrete-time linear filter; interleaved filter; offset cancellation; on-die adaptation logic; optimal receiver settings; source-coupled differential pairs; source-synchronous I/O link; transceiver; Adaptive equalizers; Clocks; Data communication; Finite impulse response filter; Intersymbol interference; Latches; Microprocessors; Mirrors; Power dissipation; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332686

Filename

1332686