Title :
A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory
Author :
Jin-Hyun Kim ; Woo-Seop Kim ; Jung-Hwan Choi ; Hong-Sun Hwang ; Changhyun Kim ; Soo-In Cho ; Suki Kim
Author_Institution :
Samsung Electron., Hwaseong, South Korea
Abstract :
A simultaneous 4-level bidirectional I/O interface for high-speed DRAM is presented. It performs at a data rate of 4Gb/s/pin with the use of a 500MHz clock generator and a full CMOS power rail swing. This I/O interface is fabricated on a 0.10μm DRAM CMOS process in 330x66μm2. The transceiver performs 200mVx690ps passing eye-windows on the channel over 1.8V supply.
Keywords :
CMOS memory circuits; DRAM chips; clocks; differential amplifiers; driver circuits; high-speed integrated circuits; transceivers; auto impedance control; clock generator; common-mode range differential amplifier; eye-diagram; full CMOS power rail swing; hierarchical selected sampling; high-speed DRAM; high-speed memory; high-speed serial links; precisely controlled transmitter block; push-pull linear output drivers; reference voltage generator; sampling performance; simultaneous bidirectional I/O; transceiver; Clocks; Differential amplifiers; Driver circuits; Frequency; Impedance; Power generation; Random access memory; Sampling methods; Transmitters; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332687
