Title :
Optimized placement of boundary scan circuitry on semi-custom ASICs
Author_Institution :
Inst. for Microelectron., Stuttgart, Germany
Abstract :
This paper presents strategies for an optimized placement of Boundary Scan test circuitry on semi-custom ASICs. It includes rules for an optimized partitioning of the BS Logic into different logical blocks as well as rules for an area-optimized implementation of these blocks. It exemplifies that Boundary Scan test of semi-custom ASICs can be feasible regardless of complexity and fabrication volume
Keywords :
application specific integrated circuits; boundary scan testing; circuit optimisation; integrated circuit layout; integrated circuit testing; logic partitioning; boundary scan test circuitry; logic partitioning; optimized placement; semi-custom ASICs; Application specific integrated circuits; Circuit testing; Decoding; Integrated circuit testing; Logic circuits; Logic design; Logic testing; Needles; Production; System testing;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580715
