DocumentCode
3413184
Title
Optimized placement of boundary scan circuitry on semi-custom ASICs
Author
Büchner, Thomas
Author_Institution
Inst. for Microelectron., Stuttgart, Germany
fYear
1995
fDate
18-22 Sep 1995
Firstpage
207
Lastpage
210
Abstract
This paper presents strategies for an optimized placement of Boundary Scan test circuitry on semi-custom ASICs. It includes rules for an optimized partitioning of the BS Logic into different logical blocks as well as rules for an area-optimized implementation of these blocks. It exemplifies that Boundary Scan test of semi-custom ASICs can be feasible regardless of complexity and fabrication volume
Keywords
application specific integrated circuits; boundary scan testing; circuit optimisation; integrated circuit layout; integrated circuit testing; logic partitioning; boundary scan test circuitry; logic partitioning; optimized placement; semi-custom ASICs; Application specific integrated circuits; Circuit testing; Decoding; Integrated circuit testing; Logic circuits; Logic design; Logic testing; Needles; Production; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580715
Filename
580715
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