DocumentCode
3413207
Title
Circuit techniques for standby mode/Iddq test compatible voltage comparators
Author
Caravella, James S. ; Mietus, David E. ; Quigley, John H.
Author_Institution
Semicond. Products Sensor, Motorola Inc., Tempe, AZ, USA
fYear
1995
fDate
18-22 Sep 1995
Firstpage
216
Lastpage
217
Abstract
This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability
Keywords
comparators (circuits); integrated circuit testing; mixed analogue-digital integrated circuits; IDDQ testing; analog circuits; data retention; digital systems; mixed signal systems; quiescent supply current testing; standby mode; voltage comparator; Analog circuits; Circuit synthesis; Circuit testing; Current supplies; Inverters; Mirrors; Power dissipation; Semiconductor device testing; System testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580717
Filename
580717
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