DocumentCode
3413209
Title
A 150MS/s 8b 71mW time-interleaved ADC in 0.18μm CMOS
Author
Limotyrakis, S. ; Kulchycki, S.D. ; Su, Donglin ; Wooley, B.A.
Author_Institution
Stanford Univ., CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
258
Abstract
This paper presents a 150 MS/s 8 bit time-interleaved ADC which has been built in 0.18 μm CMOS. Segmentation of the track-and-hold into separate circuits, driving the 1st stage comparators and two interleaved residue paths, together with signal scaling, results in a 45.4 dB SNDR for an 80 MHz input frequency, while dissipating 71 mW from a 1.8 V supply.
Keywords
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); low-power electronics; sample and hold circuits; 0.18 micron; 1.8 V; 71 mW; 80 MHz; CMOS; comparators; interleaved residue paths; signal scaling; time-interleaved ADC; track-and-hold circuits; Bandwidth; CMOS technology; Circuits; Energy consumption; Error correction; Pipelines; Quantization; Sampling methods; Signal generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332692
Filename
1332692
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