Title :
Multiple fault simulation with random and clustered fault injection
Author :
Stroud, Charles E. ; Ryan, Christopher A.
Author_Institution :
Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA
Abstract :
A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques
Keywords :
circuit analysis computing; fault diagnosis; logic CAD; logic design; logic testing; clustered fault injection; defect-tolerant design; fault detection; fault-tolerant design; gate-level multiple fault simulation; logic simulation; random fault injection; stuck-at faults; test vectors; Adders; Built-in self-test; Circuit faults; Circuit simulation; Design for testability; Electrical fault detection; Hardware design languages; Logic design; Logic testing; Research and development;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580718
