Automatic built-in self-test insertion for high level circuit descriptions

Traditionally, BIST is inserted into a circuit after the logic has been designed. This paper presents a tool that inserts BIST into high-level circuit descriptions prior to logic synthesis. We also present a novel BIST strategy called time multiplexed BIST (TMB). TMB is a method of testing sequential circuits that dispenses with one of the disadvantages of scan based methods. Scan-based testing requires serial shifting that causes increased test application time. TMB provides a compromise between fully serial and fully parallel load of all memory elements of the design. Test time is decreased compared to scan-based methods because instead of having the test patterns fed in one bit per clock cycle, TMB loads several memory elements with pseudo-random patterns during each clock cycle. Both BIST with serial scan and fully parallel load of all memory elements are special cases of TMB