A new planar stacked technology (PST) for scaled and embedded DRAMs

Author

Sim, S.P. ; Lee, W.S. ; Ohu, Y.S. ; Choe, H.C. ; Kim, J.H. ; Ban, H.D. ; Kim, I.C. ; Chang, Y.H. ; Lee, Y.J. ; Kang, H.K. ; Chung, U.I. ; Choi, C.S. ; Hwang, C.G.

Author_Institution

Semicond. R&D Center, Samsung Electronics Co. Ltd., Suwon, South Korea

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

597

Lastpage

600

Abstract

We report a Planar Stack Technology (PST) suitable for scaling and combining DRAM with logic circuits. Key features of PST technology are retrograde twin well, shallow trench isolation (STI), self-aligned poly plug structure, damascene W bit-line, Ta/sub 2/O/sub 5/ capacitor dielectric and planarized capacitor formation. This new architecture provides planar surfaces for all the lithographic steps and is easy to combine CMP-based backend processes. Although the process margin and electrical performance are proven using full density, 256 M DRAM chip, this technology can be applied to 1 G bit DRAM and beyond with simple photo lithographic scaling.

Keywords

DRAM chips; integrated circuit technology; 1 Gbit; 256 Mbit; CMP backend processing; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ capacitor dielectric; W; damascene W bit-line; embedded DRAM chip; logic circuit; photolithographic scaling; planar stacked technology; planarized capacitor; retrograde twin well; self-aligned poly plug; shallow trench isolation; Capacitors; Dielectrics; Electric breakdown; Etching; Isolation technology; Logic circuits; Planarization; Plugs; Random access memory; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.554054

Filename

554054