A performance-driven macro-block placer for architectural evaluation of ASIC designs

Author

Mori, Yutaka ; Moshnyaga, Vasily G. ; Onodera, Hidetoshi ; Tamaru, Keikichi

Author_Institution

Dept. of Electron. & Commun., Kyoto Univ., Japan

fYear

1995

fDate

18-22 Sep 1995

Firstpage

233

Lastpage

236

Abstract

This paper presents a tool for generating a performance-driven placement from a netlist of Register-Transfer Level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks such a way that to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that our tool (1) provides solutions close to those generated manually, (2) is fast enough to be used in the inner loop of a program that synthesizes RTL structures from behavioral specifications and (3) ensures strong links between RTL synthesis and timing-driven layout so necessary for design of sub-micron ASICs

Keywords

application specific integrated circuits; circuit CAD; integrated circuit layout; RTL synthesis; Register-Transfer Level blocks; circuit architecture; computer program; critical path; force-directed algorithm; performance-driven macro-block placer; submicron ASIC design; timing-driven layout; wiring delay; Adders; Application specific integrated circuits; Computational geometry; Costs; Delay; Integrated circuit synthesis; Minimization; Performance evaluation; Synthesizers; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580721

Filename

580721