Title :
Performance driven placement for cell-based designs
Author :
Natesan, V. ; Bhatia, Dinesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
Abstract :
In this paper we present a performance driven quadratic programming based placement method for large ASICs. A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing driven placement for cell based layouts. The bounds, if satisfied, guarantee correct operation of circuit for specified timing requirements. The approach has been integrated with high-level synthesis tools for generating layouts of datapaths of synthesized designs
Keywords :
application specific integrated circuits; circuit CAD; high level synthesis; integrated circuit layout; quadratic programming; timing; ASICs; cell-based designs; circuit layout; datapaths; high-level synthesis; performance bounds; performance driven placement; quadratic programming; timing; zero-slack algorithm; Contracts; Design automation; Feedback; High level synthesis; Integrated circuit synthesis; Laboratories; Quadratic programming; Solid state circuits; Timing; Workability;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580722
