DocumentCode
3413330
Title
Clock driven design method (CDDM) for deep sub-micron ASICs
Author
Tanizawa, Tetsu ; Kawahara, Sigelu
Author_Institution
Logic LSI Group, Fujitsu Labs. Ltd., Kawasaki, Japan
fYear
1995
fDate
18-22 Sep 1995
Firstpage
241
Lastpage
244
Abstract
A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsu´s 0.5 micron ASICs with no layout iteration
Keywords
application specific integrated circuits; clocks; integrated circuit layout; network routing; 0.5 micron; FF-Virtual Placement; T-Bar/Star routing; clock driven design method; clock skew; clock tree; concurrent top-down design flow; deep sub-micron ASICs; layout; Application specific integrated circuits; Clocks; Delay; Design methodology; Fixtures; Large scale integration; Logic design; Routing; Timing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580723
Filename
580723
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