DocumentCode
3413350
Title
A systematic approach to optimizing and verifying synthesized high-speed ASICs
Author
Landon, T.C. ; Salinas, M.H. ; Klenke, R.H. ; Aylor, J.H. ; McKee, S.A. ; Wright, K.L.
Author_Institution
Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
fYear
1995
fDate
18-22 Sep 1995
Firstpage
245
Lastpage
248
Abstract
This paper describes the design process used in developing a Stream Memory Controller (SMC). The SMC can reorder processor-memory accesses dynamically to increase the effective memory bandwidth for vector operations. A 132-pin ASIC was implemented in static CMOS using a 0.75 μm process and has been tested at 36 MHz
Keywords
CMOS digital integrated circuits; application specific integrated circuits; circuit optimisation; integrated circuit design; storage management chips; vector processor systems; 0.75 micron; 36 MHz; circuit optimization; design process; effective memory bandwidth; processor-memory accesses; static CMOS; stream memory controller; synthesized high-speed ASICs; vector operations; Application specific integrated circuits; Bandwidth; Control systems; Design methodology; Design optimization; Hardware; Logic design; Random access memory; Sliding mode control; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location
Austin, TX
ISSN
1063-0988
Print_ISBN
0-7803-2707-1
Type
conf
DOI
10.1109/ASIC.1995.580724
Filename
580724
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