Title :
16 Mb DRAM/SOI technologies for sub-1 V operation
Author :
Oashi, T. ; Eimori, T. ; Morishita, F. ; Iwamatsu, T. ; Yamaguchi, Y. ; Okuda, F. ; Shimomura, K. ; Shimano, H. ; Sakashita, N. ; Arimoto, K. ; Inoue, Y. ; Komori, S. ; Inuishi, M. ; Nishimura, T. ; Miyoshi, H.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit technology; silicon-on-insulator; 1 V; 16 Mbit; Cb/Cs ratio; MESA isolation; body-tied MOSFET; dual gate CMOS; floating body MOSFET; layout optimization; low voltage SOI DRAM technology; threshold voltage control; CMOS technology; Capacitors; Isolation technology; Laboratories; Low voltage; MOSFET circuits; Random access memory; Substrates; Ultra large scale integration; Voltage control;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.554057
