Title :
Performance-driven macrocell placement
Author :
Mackey, Carol A. ; Carothers, J.D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Abstract :
High performance applications in computing and communications require optimization of the VLSI hardware implementations in order to achieve the desired performance. Performance-driven macrocell placement is a key step in the process of minimizing interdevice delays and thus allowing increased performance. A quad-partitioning algorithm with a tabu search and a fuzzy cost function is proposed for optimizing macrocell placement. This is an iterative, partitioning-based approach designed to reduce path lengths and thus total delay. The results show that the addition of the fuzzy cost function as well as other improvements produce up to 43% better results than similar approaches on the test circuits
Keywords :
VLSI; circuit layout CAD; circuit optimisation; combinational circuits; delays; fuzzy logic; integrated logic circuits; iterative methods; logic partitioning; search problems; VLSI hardware implementation optimisation; communications; computing; fuzzy cost function; high performance applications; interdevice delay minimisation; iterative partitioning-based approach; macrocell placement optimisation; path length reduction; performance-driven macrocell placement; quad-partitioning algorithm; tabu search; test circuits; total delay reduction; Circuit testing; Computer applications; Cost function; Delay; Hardware; High performance computing; Iterative algorithms; Macrocell networks; Partitioning algorithms; Very large scale integration;
Conference_Titel :
Computers and Communications, 1996., Conference Proceedings of the 1996 IEEE Fifteenth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-3255-5
DOI :
10.1109/PCCC.1996.493667
