A H.264 basic-unit level rate control algorithm facilitating hardware realization

Rate control plays an important role for video coding especially in video streaming applications with bandwidth constraints. The inherent sequential processing in H.264 basic unit (BU) level rate control algorithm makes it hard to be realized in a pipelined H.264 hardware encoder without increasing the processing latency. In this paper we propose a new H.264 BU-level rate control algorithm facilitating hardware realization. The proposed algorithm breaks down the sequential processing dependence in the original rate control algorithm in JM and reduces 28% for QCIF, 66% for CIF, 87% for Dl of hardware cycles while maintaining good video quality. Simulation results shows that the proposed algorithm reduces MAD´s memory buffer size to be N_unit * 14bits, which amounts to 26% for QCIF, 59% for CIF, 83% for Dl reduction as compared to JM rate control. Moreover, the proposed algorithm possesses high feasibility for hardware realization.