Accurate estimation of power dissipation in CMOS sequential circuits

Author

Chou, Tan-Li ; Roy, Kaushik

Author_Institution

Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

285

Lastpage

288

Abstract

In this paper we present accurate estimation of signal activity at the internal nodes of sequential logic circuits. An exact method, an approximate method and a Monte Carlo based approach that take spatial and temperature correlations of logic signals into consideration are proposed. The results of the approximate and Monte Carlo based methods are within 5% and 2% of that of long run simulation, respectively

Keywords

CMOS logic circuits; Monte Carlo methods; integrated circuit design; logic design; sequential circuits; CMOS sequential circuits; Monte Carlo based approach; approximate method; exact method; extended state transition graph; internal nodes; logic signal spatial correlations; logic signal temperature correlations; low power VLSI design; power dissipation; sequential logic circuits; signal activity; CMOS logic circuits; Circuit simulation; Clocks; Combinational circuits; Driver circuits; Monte Carlo methods; Power dissipation; Sequential circuits; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580733

Filename

580733

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3413492