A FPGA Partial Reconfiguration Design Approach for RASIP SDR

A fully reconfigurable radio is a paradigm for wireless communication in which either a network or a wireless node changes its transmission or reception parameters to communicate efficiently avoiding interference with licensed or unlicensed users. Software defined radio is a common hardware platform for multi standard communication that is controlled by software. The goal of the software defined radio is to produce seamless communication devices which can support different services. Reconfigurable application specific instruction set processors (RASIP) provides complete sets of instructions for reconfiguring hardware for user specific communication interface. The terminal must adapt their hardware structure in function of the wireless network such as CDMA IS-95, GSM etc. We are proposing reconfiguration flow to validate RASIP architecture where PR (Partial Reconfiguration) is used to dynamically reconfigure the requested IP block of communication channel (i.e. CDMA IS-95 and GSM in our case). Design has been done through Model-sim 6.0b. Synthesis for actual hardware utilization on FPGA, timing analysis, bit stream generation for reconfiguration have been carried out by Xilinx ISE 9.2i. The design has been implemented on Xilinx Virtex-4(xc4vlx25-10ff668), ML401 board. This work is part of our contribution for project RASIP SDR granted by MIT, New-Delhi, India.