VHDL design and FPGA implementation of a fully parallel BCH SISO decoder

In this work, we propose a design and (FPGA) implementation of architecture of an entirely parallel SISO decoder for turbo decoding of the product codes with low complexity for high data rate applications. As an example we study a soft input/output decision decoding for the BCH (31, 26, 3) code. The VHDL design and synthesis of such architecture showed that the use of the structure combining the sub-blocks parallelism with the symbols parallelism for the establishment of such decoder can achieve a data rate of 75.5 Gb/s with low complexity, about 2199 CLBs.