Title :
A low-cost realization of multiple-input exclusive-OR gates
Author :
Lin, Kun-Jin ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Several efficient CMOS two-input exclusive-OR (XOR) logic structures have been reported in the past. Based on these XOR gates, we propose two multiple-input XOR circuit configurations, which are smaller, faster, and run at a lower power level than conventional structures formed by directly connecting two-input XOR gates. For exclusive-OR sum-of-products circuits, four transistors can be saved for each product term
Keywords :
CMOS logic circuits; delays; integrated circuit design; logic design; multivalued logic circuits; CMOS two-input exclusive-OR logic structures; XOR gate design; delay times; exclusive-OR sum-of-products circuits; low-cost realization; multiple-input XOR circuit configurations; multiple-input exclusive-OR gates; Adders; CMOS logic circuits; Circuit testing; Costs; Delay effects; Detectors; Inverters; Power dissipation; Power generation economics; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580737
