An efficient hierarchical router for large 3D NoCs

3-Dimensional Networks-on-Chip (3D NoC) are emerging as a promising solution to handle efficiently interconnects´ complexity in 3D System-on-Chip (SoC). This paper presents a new router that enables gains in terms of throughput and latency compared to classic 3D mesh the in case of large NoCs. The proposed router is hierarchical since it is composed of 2 totally decoupled modules: one for inter-layer communication and one for intra-layer communication. Throughput and latency evaluation is performed using a SystemC-TLM NoC simulator. Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Simulations´ results show that the proposed hierarchical router can outperform the 3D mesh by more than 30% in terms of throughput and latency in the case of transpose traffic.