Title :
A BiCMOS read channel two-chip combo for magneto-optical disk drives
Author :
Lee, Sang-Soo ; Laber, Carlos A.
Author_Institution :
Micro Linear Corp., San Jose, CA, USA
Abstract :
A read channel two-chip processor for rewritable 3.5" magneto-optical disk drives is presented. The front-end includes an automatic gain control (AGC) circuit, a programmable 6-pole 2-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer and a data synchronizer with 3:1 operating range to support a constant density recording with 8-24 Mbit/s data rate in 2,7 RLL format. The architecture of the chip provides a high degree of programmability through a serial microprocessor interface, fast switching (<1 μs) between sector mark and data modes, and four levels of power management in a 1.5 μm 4 GHz BiCMOS process. With a nominal power supply of 5 V, the chip set dissipates 600 mW during normal operation and 1 mW during sleep mode
Keywords :
BiCMOS digital integrated circuits; digital signal processing chips; magneto-optical recording; optical information processing; signal restoration; 1 mus; 1.5 mum; 2,7 RLL format; 3.5 inch; 4 GHz; 5 V; 600 mW; 8 to 24 Mbit/s; BiCMOS read channel two-chip processor; DC restore circuit; automatic gain control circuit; constant density recording; data synchronizer; differential ECL signal processing; fast switching; four level power management; frequency synthesizer; magneto-optical disk drives; programmability; programmable 6-pole 2-zero equiripple filter/equalizer; pulse detectors; serial microprocessor interface; sleep mode; BiCMOS integrated circuits; Detectors; Disk drives; Equalizers; Filters; Frequency synthesizers; Gain control; Magnetic separation; Magnetooptic recording; Pulse circuits;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580741
