Title :
Single chip array processor for high performance design error simulation
Author :
Kang, Sungho ; Szygenda, S.A.
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed
Keywords :
circuit analysis computing; digital simulation; errors; parallel algorithms; parallel architectures; special purpose computers; high performance accelerator; high performance design error simulation; high speed simulation; massively parallel array processor; single chip array processor; Analytical models; Circuit simulation; Computational modeling; Computer architecture; Computer errors; Computer simulation; Concurrent computing; Costs; Hardware; Logic;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580744
