A design flow for embedding the ARM processor in an ASIC

Author

Auer, Dave ; Buer, Mark

Author_Institution

VLSI Technol. Inc., Tempe, AZ, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

342

Lastpage

345

Abstract

The worlds leading chip designers and manufacturers have recently introduced several 32-bit Reduced Instruction Set Computing (RISC) processors designed for embedded applications in hopes of capturing their share of the 32-bit RISC market. VLSI Technology, a recognized leaded in ASIC design and manufacturing, offers a 32-bit RISC solution based on the ARM architecture. Embedding a microprocessor into an ASIC design presents some interesting challenges as well as offers some powerful capabilities, both of which are discussed in this paper

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; circuit CAD; integrated circuit design; logic CAD; microprocessor chips; reduced instruction set computing; 32 bit; ARM architecture; ARM processor embedding; ASIC design; RISC processor; VLSI Technology; design flow; embedded applications; reduced instruction set computing; Application specific integrated circuits; Circuit simulation; Communication system control; Manufacturing processes; Process design; Random access memory; Read-write memory; Reduced instruction set computing; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580745

Filename

580745