A method for timing driven datapath synthesis

This paper presents a datapath synthesis method that optimizes the datapath part of an ASIC design based on user specified timing constraints. Our method first synthesizes a netlist composed of datapath blocks and random logic blocks from a VHDL or Verilog RTL description of an ASIC. The datapath blocks can be implemented in bit-sliced layout, standard cells or gate-arrays. Next, for a user specified timing constraints, the bit-level slacks of each datapath block are computed using a timing verifier. If timing constraints are not satisfied, then the method finds the datapath blocks in the critical path, analyzes the area-delay trade-off of alternate architectures, and selects an appropriate architecture to improve the timing performance of the overall design. If the optimized design is not acceptable,then the user can iterate the timing constraint specification; timing verification and datapath optimization steps until an acceptable design is synthesized. Standard logic optimization techniques are also used to further optimize the control logic and datapath blocks implemented in standard cells or gate-arrays. We give examples of timing driven datapath synthesis, and discuss experimental results