A high-performance ROM compiler for 0.50 μm and 0.36 μm CMOS technologies

Author

Barry, Robert L. ; Chickanosky, John D. ; Masci, Francesco M. ; Piro, Ronald A. ; Oakland, Steven F. ; Ouellette, Michael R. ; Kemerer, Douglas W. ; Noack, Maria R. ; Leipoid, W.C.

Author_Institution

Microelectron. Co., IBM Corp., Essex Junction, VT, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

370

Lastpage

373

Abstract

A ROM compiler has been developed for use in IBM´s 0.50 μm and 0.36 μm CMOS ASIC technologies. Late-personalized mask ROMs are generated for sizes from 512 bits to 256 K bits. The 0.50 μm technology has a memory cell area of 6.40 μm² with a typical access time of 6.0 ns, while the 0.36 μm technology reduces memory cell area to 4.64 μm² and has a 4.5 ns typical access time. The ROM includes DC and AC self-test

Keywords

CMOS memory circuits; application specific integrated circuits; automatic testing; circuit layout CAD; integrated circuit layout; integrated circuit testing; read-only storage; 0.36 micron; 0.5 micron; 4.5 ns; 512 bit to 256 Kbit; AC self-test; CMOS ASIC; CMOS technologies; DC self-test; high-performance ROM compiler; late-personalized mask ROMs; memory cell; Application specific integrated circuits; Built-in self-test; CMOS technology; Clocks; Decoding; Integrated circuit interconnections; Mirrors; Read only memory; Space technology; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580751

Filename

580751