Reconfigural content addressable memory for ASIC module compiler

Author

Kim, Geunhoe ; Seo, Kwangsoo ; Lee, MoonKey ; Kang, Jungsik ; Lee, Chaemin ; Kwon, Kihong

Author_Institution

Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

1995

fDate

18-22 Sep 1995

Firstpage

374

Lastpage

377

Abstract

This paper discusses the content addressable memory (CAM) architecture for ASIC module compiler. CAM is used to perform parallel search, data search using inexact match capability, and logical operation, but a new and easy design method is required to adopt CAM in ASIC design. To generate CAMs of various architectures, research on the CAM architecture is performed. As a result, reconfigurable leaf cells and flexible floor-plan for 0.6 μm TLM CMOS are obtained

Keywords

CMOS memory circuits; application specific integrated circuits; circuit layout CAD; content-addressable storage; integrated circuit layout; memory architecture; 0.6 micron; ASIC design; ASIC module compiler; CAM architecture; TLM CMOS; data search; flexible floor-plan; logical operation; memory architecture; parallel search; reconfigurable content addressable memory; reconfigurable leaf cells; Application specific integrated circuits; Associative memory; CADCAM; Cache memory; Computer aided manufacturing; Decoding; Design methodology; Impedance matching; Logic circuits; Pattern matching;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580752

Filename

580752