Title :
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
Author :
Hung-Chi Fang ; Chao-Tsung Huang ; Yu-Wei Chang ; Tu-Chih Wang ; Po-Chih Tseng ; Chung-Jr Lian ; Liang-Gee Chen
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm2 die using 0.25μm CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128×128, code block size of 64×64, and image size up to 32K×32K.
Keywords :
block codes; discrete wavelet transforms; entropy codes; high definition television; rate distortion theory; transform coding; video codecs; video coding; CMOS technology; EBCOT architecture; HDTV resolution; JPEG2000 single-chip encoder; coding efficiency; discrete wavelet transform; encoder chip; optimized chip; rate-distortion optimization; two-bit plane parallel architecture; Bandwidth; CMOS technology; Chaos; Computer buffers; Discrete wavelet transforms; Frequency; Random access memory; Rate-distortion; Streaming media; Throughput;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332727
