Title :
An SoC with two multimedia DSPs and a RISC core for video compression applications
Author :
Stolberg, H.-J. ; Moch, S. ; Friebe, L. ; Dehnhardt, A. ; Berekovic, Mladen ; Pirsch, P.
Author_Institution :
Hannover Univ., Germany
Abstract :
An SoC is comprised of a 16-way SIMD DSP core with a 2D matrix memory, a 64b VLIW DSP core with subword parallelism, and a 32b RISC core. The 81mm2 chip is implemented in a 0.18μm 6M standard-cell technology and runs at 145MHz. The device can perform MPEG-4 Advanced Simple Profile decoding at D1 resolution, MPEG-4 encoding, and object segmentation in real-time.
Keywords :
data compression; digital signal processing chips; multicast communication; parallel architectures; reduced instruction set computing; system-on-chip; video coding; 145 MHz; 2D matrix memory; HiBRID-SoC; MPEG-4 Advanced Simple Profile decoding; MPEG-4 encoding; RISC core; SIMD DSP core; SoC; VLIW DSP core; connected component labelling; luminance-based object pixel detection; multimedia DSP; object segmentation; object tracking algorithm; standard-cell technology; subword parallelism; video compression; Arithmetic; Clocks; Digital signal processing; MPEG 4 Standard; Pipelines; Reduced instruction set computing; Registers; Signal processing algorithms; VLIW; Video compression;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332728
