An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Author

Arakawa, Fumio ; Yoshinaga, Tsunehiro ; Hayashi, Teruaki ; Kiyoshige, Y. ; Okada, Takashi ; Nishibori, M. ; Hiraoka, Toru ; Ozawa, Masayoshi ; Kodama, Tomoya ; Irita, T. ; Kamei, Toshihiro ; Ishikawa, Masatoshi ; Nitta, Yoshinori ; Nishii, O. ; Hattori, T

Author_Institution

Hitachi, Tokyo, Japan

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

334

Abstract

An embedded-processor core implemented in a 130nm CMOS process runs at 400MHz and achieves 720MIPS with a power of 250mW and 2.8GFLOPS. The processor employs a dual-issue seven-stage pipeline architecture while maintaining 1.8MIPS/MHz instruction efficiency of the previous five-stage processor. The processor is suitable for digital consumer appliances.

Keywords

CMOS digital integrated circuits; embedded systems; floating point arithmetic; microprocessor chips; pipeline processing; 2.8 GFLOPS; 250 mW; 720 MIPS; CMOS process; carry propagate adder; delayed execution architecture; digital consumer appliances; dual-issue seven-stage pipeline architecture; embedded processor core; flexible SuperH processor; flexible forwarding; floating-point instructions; load latency; on-chip RAM; real-time response; Acceleration; Cellular phones; Costs; Delay; Digital signal processing; Graphics; Home appliances; Navigation; Pipelines; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332730

Filename

1332730