A resume-standby application processor for 3G cellular phones

Author

Kamei, Toshihiro ; Ishikawa, Masatoshi ; Hiraoka, Toru ; Irita, T. ; Abe, Makoto ; Saito, Yuya ; Tawara, Y. ; Ide, H. ; Tamaki, Satoru ; Yasu, Youtaro ; Shimazaki, Yasuhisa ; Yamaoka, Masanao ; Mizuno, Hidenori ; Irie, N. ; Nishii, O. ; Arakawa, Fumio ; H

Author_Institution

Renesas Technol., Tokyo, Japan

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

336

Abstract

A 389MIPS application processor for 3G cellular phones is implemented in a 0.13μm dual-V, process. This dual-issue superscalar CPU with DSP runs at 216MHz at 1.2V and provides a resume-standby mode with a quick recovery feature using data retention of memory. The leakage current is estimated to be 98μA when the power supply is internally cut off.

Keywords

3G mobile communication; cache storage; cellular radio; digital signal processing chips; embedded systems; low-power electronics; microprocessor chips; pipeline processing; telecommunication computing; 1.2 V; 216 MHz; 389 MIPS; 3G cellular phones; 4-way set-associative instruction; DSP; data caches; data retention of memory; dual-issue superscalar CPU; leakage current; pipeline stages; pointer-controlled pipeline; quick recovery feature; resume-standby application processor; Cellular phones; Central Processing Unit; Degradation; Delay; Electronic mail; Energy consumption; Java; Leakage current; Pipelines; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332731

Filename

1332731