Title :
Parallel clocking: a multi-phase clock-network for 10GHz SoC
Author :
Nose, Keisuke ; Mizuno, M.
Author_Institution :
NEC, Kanagawa, Japan
Abstract :
The realization of SoCs operating at 10GHz and multiple frequency IP-cores is possible using parallel clocking. With 2.5GHz 4-phase parallel clocking, the skew reduction circuits and multi-phase flip-flops successfully operate at 10GHz.
Keywords :
CMOS digital integrated circuits; clocks; flip-flops; parallel architectures; system-on-chip; 10 GHz; CMOS process; SPINE clock network; SoC; clock distribution networks; local-clock network; multiphase clock-network; multiphase flip-flops; multiple frequency IP-cores; parallel clocking; parallel processing; signal integrity; skew reduction circuits; Clocks; Degradation; Flip-flops; Frequency; Jitter; Parallel processing; Reflection; Signal processing; Throughput; Wiring;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332735
