Title :
Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers
Author_Institution :
Credence Syst., Fremont, CA, USA
Abstract :
An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm2 62M transistor IC is implemented in foundry portable 0.18μm CMOS technology.
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; automatic test equipment; calibration; clocks; delay lock loops; low-power electronics; timing circuits; custom in-house transistor level design; foundry portable CMOS technology; full-featured pattern generator; high-linearity timing verniers; low linearity error; low-power timing verniers; production ATE custom processor; replica-biased DLL circuit; timing IC; vernier calibration error; Automatic test pattern generation; Calibration; Circuit testing; Clocks; Delay; Foundries; Logic testing; Production; Read-write memory; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332737
