Title :
On-chip jitter-spectrum-analyzer for high-speed digital designs
Author :
Takamiya, Makoto ; Mizuno, M.
Author_Institution :
NEC, Kanagawa, Japan
Abstract :
An on-chip jitter-spectrum analyzer (JSA) implemented in 0.18μm CMOS can locate and analyze trouble-spots in on- and off-chip power and clock distribution networks during the actual operations in the field. A feedback design-flow using JSA improves the performance of 1GHz digital LSIs.
Keywords :
CMOS digital integrated circuits; clocks; frequency-domain analysis; high-speed integrated circuits; large scale integration; spectral analysers; timing jitter; 1 GHz; CMOS implementation; actual field operation; clock distribution networks; digital LSI; feedback design-flow; high-speed LSI performance; high-speed digital designs; measurement-based calibration function; on-chip frequency-domain measurement; on-chip jitter-spectrum-analyzer; power distribution networks; Circuit noise; Clocks; Feedback; Frequency domain analysis; Jitter; Large scale integration; National electric code; Noise reduction; Power supplies; Time domain analysis;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332738
