Very fast and compact fixed template CNN realizations for B/W processing

Author

Paasio, Ari ; Kananen, Asko ; Halonen, Kari

Author_Institution

Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo, Finland

Volume

5

fYear

1999

fDate

1999

Firstpage

595

Abstract

In this paper a new approach is given for realizing fixed template CNN hardware. The proposed building blocks are digital and therefore no accuracy considerations are needed. This method is suitable for a certain type of CNN operation only. The limitations are discussed in the text. Two design examples are given, namely for the connected component detector and for the hole filler. In the simulations the circuits show very fast operation speed with the cell time constant well below 1 ns

Keywords

VLSI; application specific integrated circuits; cellular neural nets; integrated circuit design; neural chips; B/W processing; cell time constant; connected component detector; digital building blocks; fixed template CNN realizations; hole filler; operation speed; Application specific integrated circuits; Cellular neural networks; Charge coupled devices; Detectors; Electronic circuits; Guidelines; Hardware; Indium tin oxide; Laboratories; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on

Conference_Location

Orlando, FL

Print_ISBN

0-7803-5471-0

Type

conf

DOI

10.1109/ISCAS.1999.777642

Filename

777642